Conventional static timing analysis of circuit designs is done under the assumption that the delay values of circuit components are fixed at the PVT (Process, Voltage, Temperature) timing corner under consideration. However, this assumption is not correct in certain types of circuit analysis, such as analysis for deep submicron technologies. The delays of each component can vary over the die itself. For example, a component in one corner of a die may have a different delay than the same component in another corner of the die. There are delay variations across the wafer, across different wafer lots, variations due to supply voltage fluctuations across the die, etc. All of these delay variations are collectively referred to as On Chip Variation (OCV) or On Die Variation (ODV).
A simple way of incorporating these delay variations into conventional timing analysis methods is to assume (for a given timing corner) worst case delays for max paths and best case delays for the min paths. This can lead to too much pessimism because the analysis includes some delay components that have both worst-case and best-case delays at the same time.
Most of this pessimism is due to common clock paths feeding both source and destination registers of timing paths. This type of pessimism is called Common Clock Path Pessimism (CCPP) or Clock Re-convergence Pessimism (CRP). Removing or minimizing this pessimism from timing analysis is referred to as CCPP removal or CRP Removal (CRPR). CCPP removal is a hard problem in general for arbitrary clock networks. Methods to solve this problem can take an amount of time that grows exponentially with the size of the clock network.
It is in this context that embodiments of the invention arise.